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Chủ đề: Vượt qua ngăn cách giữa thế giới tương tự và số.

  1. #1
    Uỷ viên ban điều hành Box khoa ĐTVT Avatar của nothingtolose
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    Mặc định Vượt qua ngăn cách giữa thế giới tương tự và số.

    Bridging the Gap Between the Analog and Digital Worlds
    Hervé Branquart

    AMI Semiconductor

    Most applications require the co-existence of analog and digital functionality, and the benefits of combining this functionality on a single chip are significant. Such mixed-signal integration, however, also presents significant challenges. Furthermore, digital and analog developments tend to evolve at differing rates, yet mixed-signal solutions for markets such as industrial, automotive and medical, must remain available over significant time periods. The latest mixed-signal semiconductor processes are helping to address some of these issues, and this article will look at some of the issues designers should consider when specifying integrated mixed-signal solutions.

    Mixed-signal Solution for the Real World
    System designers often partition the digital portion from the analog section of a given design for a variety of reasons: the availability of mixing components for the two technologies, the complexity of the digital design or again because of the existence of pure digital processing parts as standard products. Placing the analog elements in an integrated circuit definitively allows the system designer to optimize the costs of its entire module.
    This integration approach is usually difficult for advanced markets such as telecommunications or computers, but makes sense for more mature or conservative markets such as automotive, medical and industrial. For most of these mature market's applications, digital functions are finding their way onto what once were pure analog designs. Adding digital functions to an analog design is helped in part by the development of new process technologies that can handle both short-channel, fast-switching digital transistors as well as high-voltage analog transistors. For example, AMI Semiconductor's latest mixed-signal technology offers digital and analog integration capabilities on the same design platform. The I3T technology family is based on standard CMOS 0.35µm, limiting the maximum gate voltage to 3.3V. Some consider this technology outdated, from a pure digital designer's point of view, but it is at the forefront for the automotive, industrial and medical markets.

    This list of optional features that enables the design of real SoCs includes high voltage interfacing up to 80V, microprocessing capabilities up to 32 bits, wireless capabilities up to 2.8GHz, and dense logic design up to 15K gates/mm2. Beside these capabilities, NVM integration is possible: E2PROM up to 4 Kbytes, Flash memory up to half a megabit or On-Time-Programmable (OTP) cells for application calibrations. The ability to integrate all these features on a chip gives the customer the possibility to be independent from the obsolescence of the stand-alone NVM market, which is more or less driven by the computer market. This advantage is quite relevant when we consider the cost of re-qualifying a module for the OEMs in automotive, for instance. It also makes sense when considering the long lifespan of the applications embedded into cars, the industrial environment or medical self-treatment devices where patient cost is an important consideration.
    Nevertheless bridging the gap from digital to analog on a single chip does not occur without issues. Clocking noise from high-speed digital circuits, for instance, often interferes with noise-sensitive analog functions. In addition, switching currents from high-power analog functions can interfere with low-voltage digital processors. The goal is to protect low-voltage transistors from the electric field effects of voltages that are 10 to 30 times higher.
    These important issues are not without solutions. For example, one of the latest releases in the I3T family, the I3T50 DTI, uses a deep trench isolation technique. This technique uses a series of isolating trenches that bury deep into the IC substrate; effectively creating on-chip "pockets" where noise and power supply parameters are carefully controlled.

    On top of its protection skills, the deep trench technology also helps to minimize die area by allowing dense packing of high-voltage analog pockets with low-voltage regions. You can obtain improvements in die area of 10 to 60 percent over designs that use standard junction isolation techniques.
    As mentioned earlier, the reason that system designers are using deep sub-micron technologies in those markets is often linked to the availability of devices in those technologies, not the complexity of the application itself. The complexity can be handled in many cases by an 8-bit microcontroller, or 32-bit for high-end applications. Products such as the 0.35µm I3T are able to manage the integration at a reasonable cost. A typical application diagram of a real mixed-signal SoC is shown in Figure 1.

    Figure 1: Mixed-signal SoC Diagram

    Basically, the chip integrates the system functionality from the sensor to the actuator, going through some digital processing. Conventional mixed-signal technology allows analog control and signal processing functions such as amplifiers, analog-to-digital converters (ADCs) and filters to be combined with digital functionality such as microcontrollers, memory, timers and logic control functions on a single, customized chip. All signals that process an algorithm or arithmetic calculation are digital, so conversion of analog to digital signals is mandatory when submitting data for comparison or processing by via a microcontroller, while conversion from digital output signals to analog high-voltage signals is required to drive an actuator or a load. The most recent mixed-signal technology AMIS developed, significantly simplifies the implementation of such driver functionality by allowing much higher voltage functionality to be integrated into an IC alongside the relatively low voltages required for conventional mixed-signal functions. This high-voltage mixed-signal technology is particularly relevant to automotive electronics applications where higher voltage outputs—to drive a motor or actuate a relay—need to be combined with analog signal conditioning functions and complex digital processing.

    A growing trend in mixed-signal circuit design is to add some type of central processing circuit to the analog circuits. For many applications the suitable choice of processing intelligence is an 8-bit microcontroller core such as an 8051 or 6502. 8 bits remains the most popular choice as this type of SoC is not intended to replace complex high-end central microcontrollers but more decentralized or slave applications such as sensor conditioning circuitry with local (as close to the sensor as possible) simple intelligence to control relays or motors. An automotive example would be the lateral actuation of a car's headlamps when the steering wheel is turned to improve the driver's safety and improve field of vision. The sensor input would come from the steering angle via a ****** link (most of the time with a LIN or I2C protocol) and the SoC would be close to the motor with an on-board set of algorithms to command the motor's movement.

    For higher end applications that require more calculation power, the move to ARM processors is possible. This creates a high-end solution (up to date for the mature markets) which could last over the application's lifespan because the microcontroller would be a small part of an integrated circuit that emulates the module's functionalities.
    In order to understand how larger geometries can be better suited for some mixed-signal applications, one needs to understand all of the characteristics involved. Below we will discuss seven key characteristics, however this is by no means comprehensive.

    1.Gate and memory size in mixed-signal applications generally drive cost.
    Gate and memory size drive cost because most mixed-signal devices are core limited. This can be quite different than an all digital circuit. Many times, the all digital device will have so many I/Os that the number of pads on the device determines the periphery and therefore the area. This is rarely the case for mixed-signal devices. For the most part digital cells scale pretty closely to the expected area savings. One would expect a 0.25-micron cell to be 51 percent smaller than a 0.35-micron cell of equivalent function. This is illustrated by the following formula:

    While this holds for digital cells we will see that analog cells are quite a different story. Therefore the amount of digital content (including memory) is very key in determining the best technology for the application.
    Lần sửa cuối bởi nothingtolose; 15-06-2005 lúc 02:46 AM

  2. #2
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    2.Parasitic lessens as the geometry decreases.
    This is good news for both the digital and analog designer. Understandably this will translate into high bandwidths and data rates. While the magnitude of the parasitic capacitance per gate or resistance of the interconnect is most assuredly lower as geometry decreases, it is also less predictable. This can cause analog modeling problems and highlights the need for careful understanding of the parasitic.
    3.The trans-conductance characteristic is the relationship between a drain current and the voltage across the gate and source.
    As the geometry decreases the trans-conductance gets higher. This is good news for both analog and digital domains in that smaller conductance interacts with capacitance to create smaller bandwidths and therefore lower data rates.

    It is well understood that as geometry decreases the voltage limits of the device decrease as well. In the pure digital world this is beneficial in several ways: less power and less radiated emissions. The only downside is the need for multiple voltage rails on most digital circuits. In the analog domain, the power savings is there but reduced range of operation makes the design task harder. It is quite common for analog designers to bias their circuits at VT + 2Von and Vdd - (VT + 2Von). Unfortunately, the threshold voltage, VT, does not scale with the geometry. In other words, the operating range of voltages gets smaller as the technology shrinks. This means the analog portions of a circuit must be more tightly controlled which translates to larger, better matched transistors.

    4.Channel resistance gets lower as the technology shrinks.
    While this may sound like a good thing, and for digital circuits it generally is, this translates to transistors with lower gain in the analog domain. Lower gain may mean more stages in the circuit.

    5.The linearity of smaller geometries also becomes a factor in analog designs.
    Often non-linearity problems are solved by increasing the size of the circuit. An example of this can be seen in D/A and A/D converters were the performance of the converter is very much proportional to the size of the circuit.

    6.Noise in circuits implemented in smaller technologies can become problematic for the analog designer.
    This is usually worsened by the fact that there is usually a large and fast digital circuit that is generating much of the noise. The smaller operating voltage range works against the designer as well. Signal to noise ratio in the analog circuit gets worse because the signal levels go down but the noise levels may actually go up.

    7.Analog circuit modeling in smaller geometries is problematic.
    Much of this is due to the lower levels of predictability and the nature of the parasitic. Some of it is due to the maturity of the technology as well. This, of course, will improve as the technology develops.
    Because of these items listed above it is important to understand that as the process geometry shrinks, the analog actually gets bigger, and definitely harder. This has to be compensated by increasing the sizes of the transistors, capacitors and resistors used. Moving to smaller technologies should only be done when the performance requirements of the application demand it. For most mixed-signal SoC devices this will be driven by the digital gate count and the amount of memory in the design. Only when there is significant digital content should you consider smaller technologies.
    The latest generation of mixed-signal process technologies has moved well into the deep sub-micron world where adding digital circuits and cores to an analog ASIC has become a cost-effective approach.
    With the addition of digital process capability and the digital processing horsepower that becomes available, many analog functions are being converted to digital signals earlier in the signal path. The advantage of this approach is that digital filters and digital control elements are not sensitive to drift inaccuracies caused by aging, process changes or temperature changes. The result is a much more robust design than an analog-only approach.

    About the Author
    Hervé Branquart brings a wealth of industry expertise to AMI Semiconductor as the strategic marketing manager for the automotive market.
    Banquart pioneered AMI's cultural move known as "from engineering to marketing." He holds a reputable record of company design wins and program management. Banquart was responsible for the company's first ARM-based design-win on mixed signal technology for a large U.S. industrial customer.

    Banquart's expertise in the automotive industry has been shaped by his professional leadership experience prior to joining AMIS. As product manager for Motorola Semiconductor Product Sector, he managed the development of automotive relay replacements. Additionally, Banquart directed Motorola's test support for USA automotive integrated circuits.

    Banquart earned a degree in electronic, microelectronic and software engineering at the Insitut Superieur d'Electronique de Nord. He attended the engineering school BAC for five years focusing on microelectronics, electronics, telecom, robotics, solid-state physics, image processing, microprocessor and software.

    Banquart speaks French as his mother language with a basic knowledge in English and an academic mastery of German.

  3. #3
    Uỷ viên ban điều hành Box khoa ĐTVT Avatar của nothingtolose
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    Mặc định

    Bridging the Gap Between the Analog and Digital Worlds
    Hervé Branquart
    AMI Semiconductor

    Mục đích:
    Phần lớn các ứng dụng hiên này đều tích hợp hai tính năng số và tương tự đồng thời, do vậy lợi ích của việc kết nối các tính năng này trên một chíp đơn là cần được xem xét. Đối với việc tích hợp các tín hiêu, các thách thức này cũng thể hiện rõ. Hơn thế nữa, sự phát triển của công nghệ số và tương tự có tốc độ khác nhau, cho đến nay các giải pháp mixed-signal cho thương mại công nghiệp, tự động hóa va y tế vẫn cần một thời gian phat triển đáng kể. Các quá trình xử lý bán dẫn mới nhất đang giúp cho việc xác định được các vấn đề còn gây tranh cãi, và bài báo này sẽ xem xét một vài ý tưởng mà các nhà thiết kế cần quan tâm khi thiết kế các giải pháp mixed signal.

    Nội dung :
    1. Sự phát triển của công nghệ bán dẫn áp dụng cho các mạch tương tự và số : Công nghệ xử ý bán dẫn giảm từ 0.6um ->0.5um->0.35um->0.25um->0.18u->0.13um->90nm->65nm->45nm(future) (đây là chiều dài kênh dẫn của CMOS). Các mạch tốc độ càng cao, độ tích hợp tăng lên trong khi các mạch tương tự càng khó thiết kế do chịu nhiều ảnh hưởng không thể dự đoán chính xác bằng các mô hình toán học(thiết bị kênh ngắn-short channel)

    2. Phát triển hệ thống trên 1 chip -SoC(System on Chip) :
    - Công nghệ SoC tiên tiến nhất sự kết hợp của 1 khối xử lý tín hiệu số(uC,uP,DSP ...) và bộ nhớ cùng các IC ngoại vi , tích hợp và lên kết các khối mạch tương tự với các mạch số trên cùng 1 chip cho phép thiết kế hệ thống nhanh hơn, nhỏ gọn hơn và công suât tiêu thụ giảm đi, hiệu suất hoạt động cao hơn. Do vậy cần các mạch chuyển đổi AD/DA và các bộ lọc (số và tương tự) để thực hiện việc lên kết này.

    - Sự phát triển của các hệ thống SoC cũng gắn liền với sự phát triển của khối xử lý tín hiệu, khởi nguồn từ các mạch tổ hợp logic có chức năng cố định đến các mP,mC (x84, x51-8,16 bít), và hiện nay xu hướng chú đạo la ARM (RISC 32 bít, ).

    3. 7 đặc tính cần xem xét cho hệ thống SoC :

    3.1. Kích thước của cổng logic và bộ nhớ ảnh hưởng kích thước tổng thể của SoC

    3.2. Giảm bớt hiện tượng ký sinh (tụ, điện tích) thông quả giảm kích thước hình học : (tụ kí sinh tỉ lệ thuận với độ rộng W của CMOS)

    3.3. Đặc tính của hỗ đẫn (trans-conductance) giữa dòng máng Id và điện áp Vgs : Độ tích hợp cao, đặc tính này giảm bớt dộ tuyến tính (mô hình SPICE 3, BIMSIMx), thiết kế phức tạo cần trợ giúp của các EDA tool mạnh ->chi phí cao.

    3.4. Điện trở kênh dẫn nhỏ đi khi tăng mật độ tích hợp.

    3.5. Độ tuyến tính là một yếu tố cần xem xét khi thiết kế analog khi tăng mật độ tích hợp.

    3.6. Nhiễu là một vấn đề khó giải quyết trong các thiết kế analog khi tăng mật độ tích hợp.

    3.7. Mô hình và mô phỏng các mạch analog khó khăn hơn khi tăng mật độ tích hợp.

    Tổng kết :
    - Tích hợp các mạch số và các lõi xử lý thông tin số(core) vào các mạch tương tự chuyên dụng (Analog ASIC) là một phương pháp tiếp cận hiệu quả.

    - Tích hợp các mạch số và các lõi xử lý thông tin số(core) làm tăng độ chính xác khi xử lý thông tin , khắc phục nhược điểm chính của mạch tương tự trong khi vẫn giữ lại được các ưu điểm của mạch tương tự(tốc độ cao, giao diện gắn với thực tế ...)

    Hope for interesting. NTL
    Lần sửa cuối bởi nothingtolose; 14-06-2005 lúc 06:53 PM

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