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Chủ đề: Cac bai bao ve FPGA

  1. #1
    HUT's Student
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    Nov 2004
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    Mặc định Các bài báo về FPGA

    Lâu quá rồi không post bài lên BKF. Công việc bận quá. Hàng ngày vẫn đọc bài nhưng quả thưc ít thời gian, viết một bài chất lượng thì quả thực là khó. Mình thấy công nghệ FPGA rất hay, bên khoa Điện tử bàn cái này rất sôi nổi. Mình vẫn đọc báo về cái này , thấy rất hay nên sẽ post lên đây vì thấy box này ít người tham gia quá. Ai quan tâm tới FPGA có thể vào, để tham khảo. Mình đọc thấy bài nào hay sẽ post lên

    Selecting the FPGA that Meets Your Signal Integrity Requirements

    In light of its critical nature, signal integrity needs to be a key criterion during the planning and design phases of high-speed systems. Ignoring signal integrity can lead to poor reliability, degraded performance, field failures and delayed product releases—all of which can trigger lost opportunities and revenues.

    Today’s high-end FPGAs support a variety of single-ended and differential I/O standards, with options to control drive-strength, slew-rate and on-chip termination. If not used correctly, this flexibility offered by FPGAs can make it difficult to manage signal integrity. Selecting the right FPGA that meets specific signal integrity requirements is critical for individual design success. Evaluating FPGAs requires a thorough understanding of the design methodology and features available in the FPGA to manage signal integrity, models and characterization data. This article will outline the specific information required of FPGA vendors before selecting the right device for a specific high-speed design.

    FPGA Design Methodology

    Understanding the design methodology is the first step in selecting a FPGA that meets a designer’s signal integrity requirements. Signal integrity failures in the FPGA can arise due to a variety of issues at the chip and package level. The first step is to ask vendors about their respective FPGA design methodology. Was mitigating signal integrity one of the requirements during FGPA planning and design phases? How do the vendors ensure that the signal integrity in the FPGA is robust – do they perform simulations? Knowing this information about the FPGA will provide an early indication into the emphasis placed on signal integrity.

    For example, using package-silicon co-design methodology during the FPGA design process can minimize signal integrity failures. Early in the development process, device requirements should be crafted with a keen eye on signal integrity. These requirements are used by design engineers to design I/O buffers, power-ground layout, I/O pad layout and noise isolation circuitry. Simultaneously, package engineers use these requirements to determine package technology, signal routing, power-ground distribution network and pin layout. Package and I/O buffer models are then generated.

    Using package and I/O buffer models, link level simulations are performed to ensure that performance and signal integrity requirements are met. Results from the link level simulations are used to refine the package and silicon design process. The entire package and silicon design process is now integrated and iterative, involving optimization between pin layout, chip layout and cost/performance objectives. After silicon is available, simulated data is then correlated with lab experiments. A brief flow chart of a silicon-package co-design methodology is indicated below.

    I/O Pin Capacitance
    The next step should be retrieving I/O pin capacitance data from the vendors. I/O pin capacitance significantly impacts signal integrity. High pin capacitance affects signal integrity due to reflections. At high frequencies, capacitive loading at the far end acts as a resistor with low resistance. This causes impedance mismatch on the transmission line, which in turn causes reflections. In addition, pin capacitance slows down the edge rate of the signal, reducing the data valid window. On a separate note, higher pin capacitance can have an adverse effect of system power.

    Edge Rate

    Faster edge rates are essential for reliable operation of high-speed interfaces, though they can increase simultaneous switching noise (SSN) when not properly managed. For applications not requiring fast edge rates, FPGA vendors give the option of reducing the edge rate by changing the drive strength or the slew rate settings in the programming software.

    Fast edge rates are important in applications where:

    —Available timing margin is low. Slow edge rates degrade available timing margin and have the potential to degrade interface performance.

    —High-speed memory interfaces are used. DDR2 and DDR interfaces require a minimum of 1V/ns edge rate while QDRII requires at least 2V/ns. Supporting fast edge rates is critical in these applications.

    —Load on the output is high. High capacitive loading can further slow down the edge rates, closing the signal eye. This makes it difficult for the receiver to reliably capture data.

    —Transmission line is “lossy” (signal attenuation is high), for example a long transmission line or a legacy backplane. This slows down the edge rate, impacting timing margin and signal quality at the receiver.

    On-Chip Termination

    Using the proper termination scheme is critical to maintaining good signal integrity. Improper terminations can lead to poor signal quality due to reflections or signal attenuation. Leading FPGAs offer on-chip impedance matching, series and parallel termination on single-ended I/Os and differential termination on differential I/Os. On-chip termination eliminates the need for external termination resistors on the board while minimizing reflections caused by stubs between the buffer and termination resistor. When on-chip termination is used, the resistance is not the exact, specified value. The designer needs to find out the error tolerance and whether on-chip termination impacts timing. Performing SPICE/ I/O-buffer-information-specification (IBIS) simulations will help determine the right termination for a specific design.

    Output Drive Strength and Slew Rate Control

    FPGA vendors provide programmable drive strength and/or slew rate settings for single-ended I/O standards. Using the right setting for your system helps provide the optimal signal quality and amplitude. For example, in applications where the transmission line is long or lossy, higher drive strength setting is recommended. The best way to determine the right setting for a specific application is to perform IBIS or SPICE simulations.

    Simultaneously Switching Noise

    When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. The simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or, more commonly, ground bounce. The ground bounce voltage is directly proportional to the inductance between the device ground and the system ground, and the rate of change of current (edge rate of the I/O buffer). Applications with wide-buses, such as wide-bus external memory interfaces, are particularly susceptible to SSN.

    It is imperative the designer ensures that the FPGA vendor has performed detailed SSN analysis by requesting guidelines for I/O placement and board design, as well as characterization reports, so SSN issues can be minimized.

    SPICE/IBIS Models

    The next step is to make sure the vendor has correlated I/O buffer and package SPICE or IBIS models. The vendor should have correlation data that shows the simulation results with these models match lab experiment data. Having this data proves that the vendor has done sufficient signal integrity analysis on the FPGA.

    A designer should not build a board without performing simulations to predict signal integrity within a system. While performing simulations, board trace impedance, trace length, vias, on-board termination and any other board components that will impact signal integrity have to be taken into account. This step, which is crucial in identifying potential signal integrity failures on the board, prevents expensive and time-consuming board re-spins and engineering resources required for debugging the board.
    Lần sửa cuối bởi mxktl; 01-06-2005 lúc 12:46 PM Lý do: Bổ xung

  2. #2
    HUT's Student
    Tham gia ngày
    Nov 2004
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    Mặc định

    Characterization Data

    Another issue that needs to be addressed by the FPGA vendor is in-house signal integrity characterization results. These tests should be performed under worst-case operating conditions (low voltage and high temperature). Signal integrity test data should include:

    1. Signal eye-diagrams: Eye-diagrams give a very good indication of signal quality. A good eye-opening is critical for high-speed systems. Information on I/O edge rate, jitter, duty cycle and data-valid window can be derived from the eye-diagram.

    2. I/O toggle rates: The I/O toggle rate gives the maximum I/O buffer frequency before voltage level specifications are violated.

    3. I/O pin capacitance: This indicates the quality of the buffer design. Pin capacitance should be low so signals can be properly interpreted by the receiver.

    4. Simultaneous switching noise: This test will give the amount of ground bounce and V CC sag that can be expected from the FPGA. Make sure that the FPGA vendor performs this test with 100% of the I/O bank toggling and ensure that the FPGA has passed all the SSN tests.

    5. Link level performances (for example – DDR2, QDR II, LVDS interfaces): The ultimate test for signal integrity is the robustness of link level results. Make sure that this information is made available.

    It is vital that signal integrity results of different FPGAs not be compared without first understanding the test setup. To get a proper comparison of signal integrity performance between multiple FPGAs, the designer should take into account differences in test conditions (process, voltage, and temperature), board setup, test pattern and board design guidelines (i.e., optimal board design rules for one vendor’s products are unlikely to be identical to optimal settings for another vendor’s product). Since signal integrity is very dependent on these factors, minor variations in the setup can have a significant negative impact.

    Demonstration Board

    Lastly, the designer should ask if the FPGA vendor can provide a demonstration board to perform signal integrity testing. If signal integrity test results are satisfactory, the demonstration board GERBER files should be used as a baseline for board design. Also, the FPGA vendor should be asked for termination recommendations, board guidelines, I/O placement and chip design recommendations that will reduce signal integrity issues.


    Signal integrity cannot be ignored in high-speed systems. It is imperative that designs are created with due consideration to signal integrity issues. Spending extra time up front on evaluating the right FPGA vendor for a specific system will go a long way in minimizing potential signal integrity failures.

  3. #3
    HUT's Student
    Tham gia ngày
    Nov 2004
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    Shrink-wrapping EDA
    Altium Designer Changes the Rules

    When I bought my first 10MB hard-disk drive, the salesman came to visit and even took me out to lunch. I was a freshman in engineering school and I was buying the $10,000 unit for my employer, a hotel chain, to use for storing reservation data. At the time, a purchase of that amount of mass storage was a major transaction, both for our little company and for our supplier. The disk drive, about the size of a modern desktop computer, was delivered and installed by a trained technician who spent an hour with us going over the operating procedures for the unit.

    History sometimes repeats itself a generation later. Last week, my teenage daughter bought approximately twelve times that amount of mass storage from a Target store using her leftover babysitting money. Once inside her car, she opened the shrink-wrapped plastic bubble pack, removed the tiny SD card, and dropped it into her change purse for easy access. When she needs to install it, she’ll pop open the door of her point-and-shoot digital camera, pull out the old card, and drop the new one in.

    When I got my first engineering job after college, I worked for an EDA company that sold place-and-route software to semiconductor companies. Our system cost about $250,000 and our customers did lengthy and elaborate evaluations to be sure it could handle that phase of their electronic designs. We sent trained technicians to install and monitor the operation of our software, a million or so lines of FORTRAN that sometimes buckled under the weight of 10K gate ASIC designs.

    History sometimes repeats itself a generation later. Last week, Altium Ltd. announced the availability of Altium Designer, a shrink-wrapped, complete EDA tool suite that can take complex, multi-million gate system designs all the way from concept through FPGA design and board layout. Altium Designer combines the capabilities of the company’s DXP, Protel, Nexar, Circuit Studio, and CAMtastic product lines into one low-cost, integrated environment for the electronic designer’s desktop. Protel and Nexar were each already highly integrated suites of tools, so the overall level of integration seems unprecedented in EDA.

    Altium Designer is not about exotic algorithms, faster runtimes, greater capacity, or new capabilities not previously available to electronic designers. The star of this show is the level of integration itself. Altium Designer is the “Microsoft Office” of EDA - a complete set of electronic design capabilities that can be easily and inexpensively installed on every designer’s desktop computer, facilitating every part of the design process from system-level hardware and software design through board level implementation.

    Altium’s explanation of the motivations behind Altium Designer are as intriguing as the product itself. “In the 1980s, the microprocessor revolutionized electronic design,” says Nick Martin, Altium Founder and Co-CEO. “The flexibility and power of software allowed designs to be created in a new way, where large parts of a system’s functionality could be created and modified on the fly, without redesigning hardware. We believe that FPGAs will create a similar revolution in design by dramatically increasing the amount of a system that can be made ‘soft’.”

    Altium’s tool suite is based on the supposition that designs will make increasing use of FPGAs, and that FPGAs with embedded processing capability will be the centerpiece of many systems, with complexity previously found on the board migrating into the more flexible FPGA part of the design.

    The history of EDA tools bears out this idea. Early EDA tools were built around a board-centric (and processor-centric) philosophy, with an implicit assumption that the primary complexity of the system would be captured in a schematic of interconnected board-level components. The EDA tool systems that evolved around that model included sophisticated board-level schematic capture, component library navigation and maintenance, and PCB design and layout software.

    The next generation of EDA tools were built around an ASIC-centric philosophy, with an implicit assumption that the primary complexity of the system would be contained in an ASIC, and thus captured in HDL descriptions of the ASIC portion of the design. The tool emphasis shifted to ASIC design, synthesis, simulation, verification, layout, and analysis. Board-level design was de-emphasized because complexity was migrating from the board onto the ASIC. The design and packaging of the tool suite reflected the change in the fundamental style of system design.

    Altium reckons that we are now switching from a predominantly ASIC-centric design philosophy to an FPGA-centric one. If true, the tool requirements are dramatically different from those of the ASIC-centric model. ASIC-centric design is about risk mitigation, while FPGA-centric design is about productivity, efficiency, and time-to-market. While ASIC design teams were willing to pay almost any price for tools that would increase chances for first-silicon success, FPGA teams face no financial risk comparable to the ASIC spin, and are much less inclined to pay premium prices for tools. At the same time, FPGA design and designers are far more plentiful than their ASIC counterparts, as the barriers to entry are lower and many more companies can afford an admission ticket.

    Boil all this down, and what is needed for the FPGA-centric model is a reasonably-priced, comprehensive suite of easy-to-approach, integrated tools that can work for a whole design team engaged in FPGA-based system design. Enter Altium Designer. Altium has combined their existing offerings for embedded design, FPGA design, board design, and CAM into one offering. Licensing options are available to restrict the functionality and price for engineers in various roles in the design team. The board layout specialist probably doesn’t require full access to the embedded software development tools, and the software engineer won’t be needing the Gerber files. Altium offers configurations aimed at various specialists, while retaining the notion of the tall-thin super-engineer who does everything.

    Certainly this is not the first time EDA tools have been bundled into a package, even for FPGA design. What makes this one any different, and why does integration like this have any more intrinsic value in FPGA-centric design than in board-centric or ASIC-centric design? The key is in the soft nature of the FPGA, and the implications of that softness throughout the system. As integration levels have increased and more functionality has moved into the FPGA, the interaction between board, FPGA-based hardware, embedded software, and overall system design has gotten more complex. Pinouts change regularly on the FPGA design that impact the board-level schematic and layout. Hardware design changes within the FPGA affect embedded software. System-level changes ripple quickly down through the levels of design, and because rapid development cycles mean concurrent engineering, everybody’s work affects everybody else. Integration, then, in the FPGA-centric design world, has a much higher value than in any of the previous EDA models.

  4. #4
    HUT's Student
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    Nov 2004
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    If we extrapolate the trend of the FPGA-centric system – complexity moves from the board and other devices into the FPGA itself. The board becomes essentially an FPGA with connections to the outside analog world. Most of the design team, then, is working within the soft-wired development space of the FPGA. An integrated tool suite that allows the team to coordinate their work in this dynamically changing environment becomes crucial.

    It is also interesting and appropriate that Altium is the company leading the charge in this methodology. Altium (and their previous incarnation – Protel) was built on the philosophy of offering design tools to the mainstream designer. With the shift of the EDA-market focus to ASIC-centric design, the majority of electronic systems designers were left behind. The money and technology were all being poured into ASIC, where a relatively small number of designers participated. As ASIC has evolved, that club of designers has grown steadily smaller and more demanding, soaking up the lion’s share of EDA technology development. Altium has wisely observed that the ASIC focus of the rest of the EDA market has left a vacuum in the mainstream, creating an opportunity for them to supply the remaining 90+ percent of the world’s electronic designers.

    Curiously, the only other companies aggressively pursuing this market segment, and betting on this methodology shift, are the FPGA vendors themselves. FPGA companies have long seen the need for single-source, integrated design tool suites that cater to the mainstream designer. Every FPGA vendor today supplies such a tool suite to all of their customers. There are three important differences with the FPGA vendors’ approach, however. First, FPGA companies look to gain their return on investment from silicon sales, so design tools are only a means to an end for them. Second, FPGA companies’ tool scope tends to be limited to the FPGA design itself. It does not extend up to system-level design, or down into board layout and manufacturing. Third, and most important, FPGA companies' tool suites are, by nature, proprietary and locked into each vendor’s technology.

    Because Altium is making their living on design tools, they must deliver value in the tools themselves. In the case of FPGA tools, the customer often works with the tools as a secondary consideration – a follow-on effect from choosing a particular FPGA device for their project. When tools are purchased on their own, however, the customer’s expectations are much higher, and the EDA company has to deliver on that expectation in order to stay in business. Altium argues that there is also significant value in the vendor independence of their solution. Since their offering includes a great deal of vendor-neutral IP, it is possible to create designs using Altium Designer that are not locked into a particular technology or vendor. These designs can then be migrated to various devices as technology evolves. This capability can also be used to postpone the FPGA technology decision until late in the design cycle when requirements are better known. It is even possible to try out a design using different technologies to find out, in silicon, which device works best.

    Altium’s sales process looks a lot more like mass-market software marketing than typical EDA. Obviously, if you’re planning to serve thousands or tens of thousands of customers, neither you nor your customers can afford to put a live-in applications engineer at each one. The sales and support process have to be streamlined, and the product itself has to be self-supporting and easy to approach. This is exactly what Altium has done with Altium Designer.

    While you probably won’t be picking up a shrink-wrapped copy of Altium Designer at your local software store anytime soon, this is as close as EDA has been to the approachability of consumer software products. If Altium’s vision and timing are on target, Altium Designer could be a sign of a change in the dynamics and economics of EDA, and its use could change the nature of the typical electronic product design process. The day may come when every design engineer’s standard work environment includes a PC with a comprehensive FPGA-centric design tool suite installed, in much the same way that most businesses now equip their office employees with e-mail, spreadsheet, word processing, and browser packages.

  5. #5
    svBK's Newbie
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    Dec 2005
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    Cái ma gì đây. Hiện đã có 1 công nghệ mới mang tên FPAA khá hay và hiệu quả. Hãy lên google mà tìm

  6. #6
    HUT's Student
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    FPAA=Field-Programmable Analog Array
    FPGA=Field-Programmable Gate Array

  7. #7
    Điều hành viên Avatar của hunterXhunter_1990
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    Dec 2009
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    Mặc định Re: Cac bai bao ve FPGA

    bài của bác duydt2 thì liên quan gì đến FPAA??? bác không giải thích ngày kia em sẽ del bài
    TODAY is a NEW DAY!!!!

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