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Selecting the FPGA that Meets Your Signal Integrity Requirements
In light of its critical nature, signal integrity needs to be a key criterion during the planning and design phases of high-speed systems. Ignoring signal integrity can lead to poor reliability, degraded performance, field failures and delayed product releases—all of which can trigger lost opportunities and revenues.
Today’s high-end FPGAs support a variety of single-ended and differential I/O standards, with options to control drive-strength, slew-rate and on-chip termination. If not used correctly, this flexibility offered by FPGAs can make it difficult to manage signal integrity. Selecting the right FPGA that meets specific signal integrity requirements is critical for individual design success. Evaluating FPGAs requires a thorough understanding of the design methodology and features available in the FPGA to manage signal integrity, models and characterization data. This article will outline the specific information required of FPGA vendors before selecting the right device for a specific high-speed design.
FPGA Design Methodology
Understanding the design methodology is the first step in selecting a FPGA that meets a designer’s signal integrity requirements. Signal integrity failures in the FPGA can arise due to a variety of issues at the chip and package level. The first step is to ask vendors about their respective FPGA design methodology. Was mitigating signal integrity one of the requirements during FGPA planning and design phases? How do the vendors ensure that the signal integrity in the FPGA is robust – do they perform simulations? Knowing this information about the FPGA will provide an early indication into the emphasis placed on signal integrity.
For example, using package-silicon co-design methodology during the FPGA design process can minimize signal integrity failures. Early in the development process, device requirements should be crafted with a keen eye on signal integrity. These requirements are used by design engineers to design I/O buffers, power-ground layout, I/O pad layout and noise isolation circuitry. Simultaneously, package engineers use these requirements to determine package technology, signal routing, power-ground distribution network and pin layout. Package and I/O buffer models are then generated.
Using package and I/O buffer models, link level simulations are performed to ensure that performance and signal integrity requirements are met. Results from the link level simulations are used to refine the package and silicon design process. The entire package and silicon design process is now integrated and iterative, involving optimization between pin layout, chip layout and cost/performance objectives. After silicon is available, simulated data is then correlated with lab experiments. A brief flow chart of a silicon-package co-design methodology is indicated below.
I/O Pin Capacitance
The next step should be retrieving I/O pin capacitance data from the vendors. I/O pin capacitance significantly impacts signal integrity. High pin capacitance affects signal integrity due to reflections. At high frequencies, capacitive loading at the far end acts as a resistor with low resistance. This causes impedance mismatch on the transmission line, which in turn causes reflections. In addition, pin capacitance slows down the edge rate of the signal, reducing the data valid window. On a separate note, higher pin capacitance can have an adverse effect of system power.
Faster edge rates are essential for reliable operation of high-speed interfaces, though they can increase simultaneous switching noise (SSN) when not properly managed. For applications not requiring fast edge rates, FPGA vendors give the option of reducing the edge rate by changing the drive strength or the slew rate settings in the programming software.
Fast edge rates are important in applications where:
—Available timing margin is low. Slow edge rates degrade available timing margin and have the potential to degrade interface performance.
—High-speed memory interfaces are used. DDR2 and DDR interfaces require a minimum of 1V/ns edge rate while QDRII requires at least 2V/ns. Supporting fast edge rates is critical in these applications.
—Load on the output is high. High capacitive loading can further slow down the edge rates, closing the signal eye. This makes it difficult for the receiver to reliably capture data.
—Transmission line is “lossy” (signal attenuation is high), for example a long transmission line or a legacy backplane. This slows down the edge rate, impacting timing margin and signal quality at the receiver.
Using the proper termination scheme is critical to maintaining good signal integrity. Improper terminations can lead to poor signal quality due to reflections or signal attenuation. Leading FPGAs offer on-chip impedance matching, series and parallel termination on single-ended I/Os and differential termination on differential I/Os. On-chip termination eliminates the need for external termination resistors on the board while minimizing reflections caused by stubs between the buffer and termination resistor. When on-chip termination is used, the resistance is not the exact, specified value. The designer needs to find out the error tolerance and whether on-chip termination impacts timing. Performing SPICE/ I/O-buffer-information-specification (IBIS) simulations will help determine the right termination for a specific design.
Output Drive Strength and Slew Rate Control
FPGA vendors provide programmable drive strength and/or slew rate settings for single-ended I/O standards. Using the right setting for your system helps provide the optimal signal quality and amplitude. For example, in applications where the transmission line is long or lossy, higher drive strength setting is recommended. The best way to determine the right setting for a specific application is to perform IBIS or SPICE simulations.
Simultaneously Switching Noise
When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. The simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or, more commonly, ground bounce. The ground bounce voltage is directly proportional to the inductance between the device ground and the system ground, and the rate of change of current (edge rate of the I/O buffer). Applications with wide-buses, such as wide-bus external memory interfaces, are particularly susceptible to SSN.
It is imperative the designer ensures that the FPGA vendor has performed detailed SSN analysis by requesting guidelines for I/O placement and board design, as well as characterization reports, so SSN issues can be minimized.
The next step is to make sure the vendor has correlated I/O buffer and package SPICE or IBIS models. The vendor should have correlation data that shows the simulation results with these models match lab experiment data. Having this data proves that the vendor has done sufficient signal integrity analysis on the FPGA.
A designer should not build a board without performing simulations to predict signal integrity within a system. While performing simulations, board trace impedance, trace length, vias, on-board termination and any other board components that will impact signal integrity have to be taken into account. This step, which is crucial in identifying potential signal integrity failures on the board, prevents expensive and time-consuming board re-spins and engineering resources required for debugging the board.